A monolithic 2.3 Gb/s 100 mW clock and data recovery circuit

A PLL (phase-locked-loop)-based clock and data recovery chip intended for several data-link applications above 2 Gb/s is described. The single-chip clock and data recovery PLL is implemented in a standard digital silicon bipolar technology without modification. The only external component is the loop filter capacitor. At 2.3 Gb/s, the chip consumes 100 mW from a-3.6-V supply, excluding the input and output buffers. This enables integration of these functions into a larger receiver subsystem while still keeping the power dissipation low. The ground rules used in this work result in an n-p-n device with 0.7 mu m effective emitter width and peak fT of about 30 GHz.