Publication
IEEE JSSC
Paper

A Josephson Latch

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Abstract

A latch has been developed which is suitable for use in a high-speed Josephson latching-logic computer. Measurements on a test chip incorporating latch circuits have shown that the flip-flop is capable of changing states in ~120 ps and that races can be prevented by deriving timing information from the ac power waveform. Details of the design and experimental results are given. Copyright © 1978 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1978

Publication

IEEE JSSC

Authors

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