IS&T/SPIE Electronic Imaging 2013
Conference paper

A GPU based implementation of Direct multi-bit search (DMS) screen algorithm

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In this paper, we study the feasibility for using programmable Graphics Processing Unit (GPU) technology for image halftoning, in particular implementing the computationally intense Direct Multi-bit Search (DMS) Screen algorithm. Multi-bit screening is an extension of binary screening, in which every pixel in continuoustone image can be rendered to one among multiple output states. For example, a 2 bit printer is capable of printing with four different drop sizes. In our previous work, we have extended the Direct Binary Search (DBS) to the multi-bit case using Direct Multi-bit Search (DMS) where at every pixel the algorithm chooses the best drop output state to create a visually pleasing halftone pattern without any user defined guidance. This process is repeated throughout the entire range of gray levels while satisfying the stacking constraint to create a high quality multi-bit screen (dither mask). In this paper, we illustrate how employing Graphics Processing Units (GPU) can speed-up intensive DMS image processing operations. Particularly, we illustrate how different modules can be been parallelized. The main goal of many of the previous articles regarding DBS is to decrease the execution time of the algorithm. One of the most common approaches is to decrease the neighborhood size or filter size. The proposed parallel approach allows us to use a large neighborhood and filter size, to achieve the highest halftone quality, while having minimal impact on performance. In addition, we also demonstrate processing several non-overlapping neighborhoods in parallel, by utilizing the GPU's parallel architecture, to further improve the computational efficiency. © 2013 SPIE-ISandT.