A fast physical constraint generator for timing driven layout

Abstract

A fast procedure to generate physical (capacitance, resistance, RC) constraints and timing weights for timing driven physical design is presented. When the capacitance of the nets and the resistance/RC delay of the source-sink segments of the layout are not bigger than the corresponding constraints, the timing requirements can be met. The main results are: a) a fast procedure with linear run-time in the number of pins in the design, b) controlling wire delay due to wire resistance, and c) fast interaction between physical design and timing analysis for timing and wirability control.