A 400Mb/s clock and data recovery PLL system in a 0.5UM CMOS asic process

Abstract

The design of a phase locked loop (PLL) system for clock and data recovery (CDR) on a 400Mb/s serial data stream was described. The CDR system was designed for a node bypass circuit function within a disk file subsystem, which used the SSA 2 interface to connect between individual devices. An eye diagram at the receiver input showed that the data rate of 400Mb/s and the jitter was obtained due to the cable interconnect from the remote transmitter. It was found that the four data recovery PLL systems on NBC chip operate independently of each other without significant coupling between them. The disk was successfully integrated into a disk subsystem supporting dual speed operation at 200Mb/s and 400Mb/s.