IBM at the APS Global Physics Summit 2026

Quantum processors with error mitigation are becoming powerful tools for exploring the non-equilibrium dynamics of many-body systems. Generic quantum dynamics often result in quickly vanishing correlation, making it difficult to resolve in present experiments. Here, we present a novel model employing perturbed mirror circuits to study complex dynamics in a quantum many-body system. These circuits retain large correlation while still challenging several classical simulation algorithms, including tensor-network and Pauli propagation methods. This positions the model as a realistic and physically motivated benchmark for the performance of quantum and classical simulation methods. In these talks, we shall present details of our model, showcase classical benchmarking of the circuits, and discuss experimental results from IBM quantum processors.

Speaker: Vinay Tripathi

Achieving reliable quantum computation on noisy intermediate-scale devices requires robust quantum error mitigation (QEM) methods with controllable accuracy. However, most existing QEM techniques either rely on explicit noise characterization or leave residual bias that is difficult to quantify. We introduce CAESER (Circuit Average Ensemble Series Expansion Rescaling), a noise–model-free QEM protocol that provides bounded and systematically reducible bias for arbitrary quantum circuits. CAESER leverages the Clifford Perturbation Theory (CPT) representation of a target circuit to construct a classically simulatable ensemble of Clifford circuits whose expectation values can be combined with quantum measurements to estimate and correct residual bias. This hybrid quantum + HPC approach yields a provably asymptotically unbiased estimator without requiring noise learning or circuit-structure constraints. We experimentally demonstrate CAESER on large-scale random mirror circuits and Hamiltonian time-evolution benchmarks using IBM Heron quantum processors, showing significant accuracy improvements over both unmitigated and classically simulated results. CAESER exemplifies a general Boosted Error Mitigation framework that systematically improves the fidelity of error-mitigated observables, paving the way for an asymptotically bias-free quantum computation in the pre-fault-tolerant era.

As quantum hardware and software improves towards advantage and beyond, well-designed full stack benchmarks are critical for gauging progress. Such benchmarks must be designed to proxy for value in applications of interest, inform on the impact of new capabilities, and track low-level system improvements. At the same time, benchmarks must be practical; a benchmarking suite must keep usage at a reasonable level so that it can be run frequently and without monopolizing the device. With that in mind, we are developing a benchmarking suite that probes quantum computers along the three cores axes -- functionality, quality, and timing. The suite answers three relevant questions along these axes: (1) Are hardware and software capabilities, such as dynamic circuits and advanced error mitigation methods, working as expected? (2) Is the fidelity of the benchmarks improving with newer generations of hardware and software? and (3) Are quantum circuit execution times improving? The notion of scale is explicit as the benchmarks are defined at different widths and depths as allowed by the state of the hardware. The suite consists of utility-scale algorithms and applications from chemistry, physics, and optimization, as well as widely accepted benchmarks such as GHZ state generation, whilst aiming to keep QPU usage at a reasonable level. As IBM's hardware and software ecosystem continuously evolves, we have included forward looking tests that will evaluate new capabilities along IBM's roadmap when they become available, and will provide us with clear comparisons across multi-generational device architectures.

As modern quantum processors have pushed to larger scales and lower error rates, the task of low-level device benchmarking has grown in complexity. While there are established protocols to report simple metrics such as qubit coherence and error rates from randomized benchmarking (RB), these cannot adequately characterize devices at scale and track hardware improvements. For example, RB reports error rates without circuit structure or crosstalk. Furthermore, modern devices have added features such as enhanced gatesets involving non-Clifford “fractional” two-qubit gates and feedforward operations (dynamic circuits). Therefore, to characterize our devices, we have developed a toolbox of methods to enable full coverage. While we start with standard RB, we build on that with purity RB, then layer fidelity (RB in structured layers) [1,2], Bell tests for fractional and dynamic circuits and RB protocols that include mid-circuit measurement [3] and dynamic circuits [4].

In this talk, we will discuss the principles behind each protocol, demonstrate how they enable us to build a full device health view, and share data from recently deployed systems highlighting the progress achieved across successive system generations.

A central challenge in evaluating proposals such as the fault-tolerant qLDPC architecture introduced in Tour de Gross [1] is to predict performance in the extremely rare-failure regime required for large-scale quantum computation, where Monte Carlo simulation becomes infeasible. This talk will present the analytical and numerical techniques developed in [2] and applied in [1]. We outline three complementary techniques that together yield consistent predictions of logical error rates far below the reach of standard sampling. The focus of the talk will be on the conceptual foundations of these techniques: why they work, the conditions that govern their validity, and how they enable the evaluation of next-generation quantum LDPC codes and other architectures beyond the limits of brute-force Monte Carlo simulation.

Quantum error mitigation can enable noisy quantum processors to produce unbiased estimates of observable expectation values, at a runtime cost exponential in the noise rate. Novel error mitigation methods have emerged that leverage classical compute resources to reduce error mitigation overhead, at the expense of classical runtime and controlled error. Pauli propagation has gained interest for classically simulating certain problems such as near-Clifford circuits, and can naturally leverage the sparsity of Pauli-based noise models. Here, we present a hybrid workflow for Pauli propagation that relies on the forward propagation of inverse noise channels classically, and the measurement of a modified observable on a quantum computer. We study the validity and viability of such classical Pauli propagation for error mitigation, including numerical and experimental results, and open-source software tools.

Peaked circuits are quantum circuits engineered to concentrate probability weight on a single bitstring, offering a practical path to verifiable quantum advantage because experimental quantum sampling distributions can be efficiently checked. We implement peaked-circuit sampling on IBM superconducting quantum processors and compare the performance to various classical simulation strategies. To handle realistic noise, we introduce a mitigation strategy tailored to peaked sampling distributions that boosts recovery of the target peak. By comparing hardware and classical on identical circuits, our benchmarks point to experimentally accessible regimes where verifiable quantum advantage may emerge.

Quantum computers may help solve combinatorial optimization problems more efficiently than classical computation alone. In this work, we explore the application of quantum-enhanced Markov chain Monte Carlo (QeMCMC), originally developed for approximating challenging probability distributions, in the context of combinatorial optimization. We focus on Maximum Independent Set (MIS), a class of combinatorial optimization problems known to be difficult to solve with state-of-the-art classical solvers for relatively small system sizes. Non-trivial instances of these are provided by the Quantum Optimization Benchmarking Library. More specifically, we combine heuristics of QeMCMC with parallel tempering, a method used to find ground states of many body systems, to tackle MIS graph problems with more than 100 decision variables. In the original work of Layden et al., QeMCMC showed promise as a near-term sampling algorithm with tangible resilience to noise. Our work applies QeMCMC to practical optimization applications and demonstrates the capabilities of existing and near-term quantum computers to solve hard, relevant optimization problems at scale. We present the success of our algorithm in solving a 123-node problem using 123 qubits on IBM quantum hardware. Finally, supported by analysis of what can be achieved with access to larger devices and improved error-rates, these results help build a clearer path to finding advantage in optimization for quantum computing.

Last year, we debuted the bicycle architecture [1], a modular quantum computing framework which performs universal, fault-tolerant quantum computation on information encoded into bivariate bicycle codes. As a first of its kind quantum computer employing high-rate, low-density parity-check (LDPC) codes and generalized code surgery, we anticipated the blueprint to evolve based on further research. Here, I will review the design principles and advantages of the bicycle architecture, including its low qubit overhead and flexibility, and present updates, including new benchmarking results. In parallel, IBM is excited to be making quantum LDPC codes a reality in superconducting hardware, and I will present some updates from that effort.

At IBM Quantum we have iterated over multiple generations of 100+ qubit systems (Eagle, Osprey, Heron, Crossbill, Nighthawk) with a continued focus on building larger systems. As part of this effort our readout hardware has evolved to meet both scaling requirements and performance requirements to build out these systems. One aspect of this evolution is how we design, package and place traveling wave parametric amplifiers (TWPA's) in our readout chain. At the device design level, we look to improve loss and suppress unwanted parametric processes as both have down stream impacts on system dynamic efficiency. These design considerations include adjusting the capacitor layout, resonator layout and the dispersion profile of the TWPA. At the system integration level, we look to tightly integrate other passive microwave components required for TWPA operation. For example, placing filters in an integrated package to impedance match across signal and idler bands and minimize insertion loss. This approach allows us to improve gain and efficiency realizing more performant amplification in our readout chain.

Large variations in the energy relaxation time (T1) of superconducting qubits makes it difficult to accurately evaluate and compare new qubit materials and fabrication processes, or to perform studies that require precise measurements of energy loss. To address this issue, we present techniques for characterizing qubit quality factors with voltages applied to electrodes in the vicinity of the qubit. A number of different experiments are reviewed which demonstrate how a TLS voltage electrode can be used to accelerate and improve learning about qubit coherence.

Decoherence and gate errors lead to faulty quantum computation. While quantum error correction is widely regarded as the only known path to realizing the full potential of quantum computing, it has yet to be implemented at scale on current hardware platforms. This raises a central question: What can one achieve with existing, noisy quantum processors before the advent of fault tolerance? I will discuss how this question motivated the development and implementation of error mitigation techniques to perform reliable quantum computation on current processors. I will present the historical development of these experiments, the current state and impact of these techniques, and their relevance as devices advance toward the fault-tolerant era.

Sample-based quantum diagonalization (SQD) approximates many-body ground states by classically diagonalizing Hamiltonians in subspaces generated from samples produced on a quantum processor. Building on the Sample-based Krylov Quantum Diagonalization (SKQD) variant — which constructs Krylov subspaces from time-evolution circuits and guarantees convergence under the assumption of a concentrated ground-state wave function — we address a key limitation: the large circuit depth required to generate Krylov states for realistic chemical Hamiltonians.

We introduce SqDRIFT, a randomized version of SKQD that replaces coherent time evolution with a qDRIFT-style stochastic compilation of the propagator. This approach preserves the convergence guarantees of SKQD while substantially reducing circuit depth and mitigating hardware noise. We apply SqDRIFT to compute the electronic ground-state energies of polycyclic aromatic hydrocarbons, achieving accurate results for molecular sizes beyond the reach of exact diagonalization. These findings highlight SqDRIFT as an efficient and robust approach for quantum-enhanced electronic structure calculations.

Speaker: Samuele Piccinelli

We present recent theoretical and experimental results on sample-based Krylov quantum diagonalization (SKQD). SKQD provides a framework for attaining formally provably convergence for quantum simulation of ground state energies, provided the Hamiltonian, ground state, and initial reference state satisfy certain criteria similar to those of quantum phase estimation. Results of an SKQD experiment are variational and classically verifiable, providing a potential path to certifiable quantum advantage.

Estimating observables is a central task in quantum simulation, and today's quantum processors can already implement circuits whose observable values lie beyond the reach of certified classical simulation. In this regime, only classical heuristics are available, raising a fundamental question: how do we build trust in the outcomes of quantum computation? In this talk, I will present an experimental study of operator dynamics in a family of structured circuits that challenge several leading classical simulation methods. We employ and compare observable estimates from multiple quantum experiments, using both heuristic and rigorous error-mitigation techniques, to establish confidence in the results of quantum simulation.

Fault-tolerant quantum computing demands scalable innovation across all quantum system layers, particularly in control electronics, where size, power consumption, and deployment costs must be significantly reduced versus today’s solutions. We present the first large-scale demonstration of cryogenic CMOS (cryo-CMOS) control for superconducting qubit quantum systems within a hybrid architecture that combines cryogenic flux control ASICs with room-temperature RF electronics for qubit drive, readout, and state discrimination.

The system integrates multiple cryo-CMOS ASICs, each supporting 16 independently programmable flux channels, comprised of a microcontroller and an associated high-precision DACs, enabling low-noise, low-power flux biasing optimized for high-fidelity two-qubit gates. The ASICs are housed in multi-chip packages, compatible with high-density flex ribbons, and thermally anchored to a dedicated cryo-cooler.

This hybrid control solution is deployed on IBM’s 156-qubit Heron R2 processor and characterized across a broad range of operating conditions—including thermal stability, signal integrity, and noise performance—demonstrating model-to-hardware alignment with system design targets. These results establish the viability of the hybrid architecture as a path to achieving required reduction in size, power consumption, and costs central to delivering fault-tolerant superconducting qubit-based quantum computing solutions.

Scaling toward large-scale and fault-tolerant quantum computing requires overcoming engineering challenges across the entire quantum system, particularly in qubit control infrastructure. For example, superconducting quantum processing unit (QPU) architectures based on quantum low-density parity-check (QLDPC) codes demand significantly more flux-tunable couplers than physical qubits. In this context, we present the first demonstration of a scalable cryogenic quantum control system element comprised of an array of multi-channel cryo-CMOS flux bias control chips, connected to the majority of flux-tunable couplers on IBM's 156-qubit Heron R2 QPU. Two-qubit gates performed using cryo-CMOS achieve a median randomized benchmarking error per gate of ~2.3x10-3, comparable to that achieved using room temperature electronics with the same QPU. Additional experiments demonstrate that cryo-CMOS operates with low noise and high stability across various configurations and temperatures. Finally, we validate full-stack integration through the Qiskit interface, culminating in an at-scale benchmarking experiment on par with IBM's highest-performing deployed quantum systems.

Join me for a talk about my career path in quantum computing, from characterizing quantum devices to exploring what's possible with quantum technology. I'll share my experiences working in this rapidly evolving field and describe the latest advancements at IBM Quantum. as well as opportunities and challenges in the field. As quantum computing emerges as a powerful tool for scientific discovery, I'll offer my perspective on the most exciting prospects in this new era.

Quantum Extreme Learning Machines (QELM) exploit the rich dynamics and high-dimensionality of Hilbert spaces, together with design principles inspired by Reservoir Computing, to offer a promising path for large-scale quantum machine learning. However, most prior work has focused so far on analog implementations or numerical simulations, with practical deployment often hindered by device noise and concentration of measure effects.

In this work, we propose a scalable QELM architecture tailored for state-of-the-art digital quantum processors. Our design combines theoretical rigor with experimental feasibility, aiming to preserve model expressivity while mitigating the impact of observable concentration and shot noise. Central contributions include a practical hyperparameter tuning strategy that identifies optimal operating regimes balancing robustness and processing capacity, as well as a local signal-to-noise ratio optimization method based on eigentask analysis.

We validate our approach on paradigmatic benchmark tasks, demonstrating strong performance and noise resilience using up to 124 qubits on IBM Quantum processors. By tracking key indicators such as output variability and expressivity, we uncover a universal regime that generalizes across tasks and system sizes.

Adaptive monitored quantum circuits that perform reset via conditional feedback based on mid-circuit measurements allow for non-unitary evolution on programmable quantum computers. We study control induced phase transitions in a Bernoulli circuit using IBM's superconducting qubit based quantum computers. This map scrambles quantum information, while conditional feedback steers the dynamics toward an absorbing state. This competition drives a dynamical phase transition between chaotic to controlled dynamics, and quantum to classical dynamics. Applying up to nearly 5000 entangling gates and 5000 non-unitary mid-circuit operations on systems up to 100 qubits, we faithfully reproduce both the chaotic-to-controlled and quantum-to-classical phase transitions. Estimates of the universal critical properties are obtained to high accuracy and experimental results are benchmarked against various numerical simulations.

We propose a hybrid quantum-classical algorithm for approximating the ground state of two-dimensional (2D) quantum systems using an isometric tensor network (isoTNS) ansatz. Inspired by the density matrix renormalization group, we optimize the isoTNS sequentially by diagonalizing a series of effective Hamiltonians. The latter are constructed with a quantum-computing algorithm that first represents the isoTNS as a quantum circuit and, then, applies a tomography-inspired method. The first step can be performed efficiently because the tensor network is composed of isometries, which can be naturally embedded within unitary operations that are then mapped to quantum gates. The classical cost of the second step remains manageable because the tomography is applied on a number of qubits that depends only on the bond dimension. By leveraging quantum computers, our approach does not rely on approximate contractions that are used to reduce the computational cost of classical 2D TNS methods. Moreover, it circumvents the exponential complexity of classical techniques through quantum computations. We demonstrate our method on the 2D transverse-field Ising model, achieving ground-state optimization on up to 25 qubits with modest quantum overhead (in terms of both circuit depth and number of shots) -- significantly less than solutions based on variational quantum eigensolvers. Overall, our results offer a path towards scalable variational quantum algorithms in both utility and fault-tolerant regimes.

We present a new heuristic decoder, Relay-BP, targeting real-time quantum circuit decoding for large-scale quantum computers. Relay-BP achieves high accuracy across circuit-noise decoding problems: significantly outperforming BP+OSD+CS-10 for bivariate-bicycle codes and comparable to min-weight perfect matching for surface codes. A core aspect of our decoder is its enhancement of the standard BP algorithm by incorporating disordered memory strengths. This dampens oscillations and breaks symmetries that trap traditional BP algorithms. By dynamically adjusting memory strengths in a relay approach, Relay-BP can consecutively encounter multiple valid corrections to improve decoding accuracy. We observe that a problem-dependent distribution of memory strengths that includes negative values is indispensable for good performance. We conclude with recent progress on implementing Relay-BP in FPGAs for accurate real-time decoding of quantum memory experiments.

The introduction of quantum low-density-parity-check (qLDPC) [1] codes promises to significantly decrease the overhead associated with quantum error correction. This decrease, however, comes at the expense of device complexity. qLDPC devices require connectivity beyond 2D and often require this connectivity to be long-range. In this talk, I will review the progress made by the IBM team in realizing the necessary elements of this architecture, such as a demonstration of high connectivity, long-distance couplers, couplers that break out of the plane, and the ability to actively reset qubits. I will review how these elements will be integrated into the Loon quantum chip, the first qLDPC prototype.

The career paths available to physicists are becoming increasingly diverse, yet the transition from academia to industry often remains uncertain for many early-career researchers. In this talk, I will share some observations from my own experience moving from academic to industrial research in the field of quantum computing. After completing a Ph.D. at the University of Tokyo, where I worked on superconducting quantum circuits, I spent a short period as a postdoctoral researcher at the RIKEN Center for Quantum Computing before joining IBM Thomas J. Watson Research Center. Through these experiences, I have come to appreciate both the common foundations and the distinct challenges of research in academia and industry. I will discuss how the focus, collaboration style, and measures of success can differ between the two settings, and how skills developed through a Ph.D.—such as critical thinking and experimental discipline—remain valuable across them. My hope is that by sharing an early-career perspective, this talk can contribute to an open discussion about the variety of meaningful and impactful paths that physicists can pursue beyond academia.