Chemical vapor deposition (CVD) and chemical-mechanical planarization (CMP) of tungsten have been the enabling process technologies for semiconductor manufacturing. Despite the long history and relative maturity, however, their combined effects on the electrical performance and topographic variation of W metallization are scarcely reported in the open literature. A previous work on Cu plating demonstrates the feasibility of reducing topography and improving electrical resistance uniformity by manipulating Cu plating process for superior incoming filling across different patterns and line widths within the die. Adopting the similar concept, this study utilizes SiH4 and WF6 gas chemistry in a CVD-W process optimized for reduced seam formation. 300 mm wafers with varying W overburden thickness are deposited and polished in order to examine the impacts on resulting resistance uniformity across different line widths, and within-die topography. It will be demonstrated that CVD W overburden thickness alone plays a critical role in the performance of W local interconnects across patterns of varying geometry and feature size. Thicker incoming overburden thickness can improve CMP process window and help mitigate variations in sheet resistance plus local and within-die topography, which can perpetuate during down-stream process and impact device performance adversely. Co-optimization of CVD-W and WCMP processes is pivotal to the performance of W metallization.