Yichen Xu, Baoqi Zhu, et al.
VLSI Technology and Circuits 2026
This work explores the challenges and capabilities for utilizing high-NA EUV lithography to pattern both damascene Cu interconnects and subtractive Ru interconnects. We explore potential solutions through OPC and mask optimization to enable patterning for similar structures for damascene and subtractive structures. A comparison of LER, defectivity and electrical characterization is done for a direct comparison between damascene and subtractive structures.
Yichen Xu, Baoqi Zhu, et al.
VLSI Technology and Circuits 2026
Lin Dong, Steven Hung, et al.
VLSI Technology 2021
Alex Hubbard, Christopher Carr, et al.
SPIE Advanced Lithography + Patterning 2026
Akihiro Horibe, Yoichi Taira, et al.
IEDM 2025