Genesys-Pro is an industry-leading state-of-the-art test program generator for processor and multi-processor functional verification. Genesys-Pro:
- Provides an efficient means for creating architectural tests that implement verification plans
- Enables users to specify the desired extent of randomness in the generated tests, ranging from completely deterministic to totally random
Genesys-Pro is a primary solution for verification teams seeking an effective and sustainable solution for the verification of large-scale industrial processor designs. These demand tool customization abilities, concurrent support of multiple designs, and support for complex architecture and micro architectural features such as multi processor coherency, VLIW, floating point, and address translation.
The ever-growing demand for performance and time-to-market, coupled with the exponential increase in hardware size, has made the verification task increasingly difficult. This problem is exacerbated by low tolerance for bugs in CPU designs.
The elusive nature of hardware bugs and the amount of stimuli needed to cover the scenarios specified in the verification plan, has made directed random stimuli generation the verification approach of choice.
Former solutions, including directed testing and hand-tailored project-specific generators, are not scalable to today's challenges.
Commercial verification environments have added constructs to support reuse and random generation. However, effective application of these generic features to processor verification requires significant investment in infrastructure and methodology.
Genesys-Pro was specifically designed to address the challenges of test case generation for processor and multi-processor verification.
The tool is based on a generic engine that receives as input:
- Test specification - describes a verification scenario
- Design model - describes the design architecture and micro-architecture
The design model is specified in a declarative language that contains special constructs for describing the architecture and micro-architecture-including instructions, registers, cache structure, and translation mechanisms.
The test scenario is specified in a programming-like language, with special constructs for specifying biased random scenarios involving stimuli for one or more processors.
The restrictions specified by the test template and the design model are automatically translated into constraints on the output test.
Example test template
A dedicated graphical IDE allows the rapid development and debugging of test scenarios. The interface was designed to allow simple scenario definition for the casual user while still providing full capabilities for experts. It relieves users from having to remember language syntax and access off-line documentation.
Genesys-Pro can also bias the tests into triggering interesting architectural and micro-architectural events that are likely to expose design bugs.
The generic engine employs a powerful constraint satisfaction problem (CSP) solver especially tuned to the characteristics of the resulting CSP. This helps obtain a test that conforms to the scenario, the architectural restrictions, and many biases.
Genesys-Pro is also integrated with two deep-knowledge test generators, FPgen and DeepTrans. This allows Genesys-Pro to create sophisticated and difficult to create scenarios in the areas of floating point and memory management unit (MMU) verification.
Genesys-Pro uses a reference model to track the state of the processor throughout the test generation. The tool can then adapt the generation based on the state of the processor and report the expected results.
By customizing the design model, Genesys-Pro is able to support all variants of the Power architecture as well as other architectures, ranging from ARM to the mainframe zArchitecture.
- Novel cost-saving paradigm driven by an innovative processor-oriented language to define verification scenarios
- Built-in testing knowledge to reach interesting bug-prone events
- Customizable to all variants of Power architecture and other architectures
- Employs best-in-class constraint satisfaction engine
- Leverages two decades of experience in test generation and verification
- Supports both multi-processing and multi-threading
Impact on IBM
Genesys-Pro has become the standard processor-level test generator within IBM for Power and System Z designs. It has been used in the development of virtually all IBM PowerPC processors, ranging from embedded processors to i/p-series server systems, the Cell, and the Microsoft Xbox core processors. Genesys-Pro was also used in the verification of non-PowerPC cores, such as the Cell's Synergistic Processing Unit (SPU).
IBM estimates that it has saved more than $100 million during the last decade in direct development costs and reduced time-to-market by employing the Genesys-Pro verification technologies. The exceptional impact it made on the verification of IBM designs earned Genesys-Pro the IBM Outstanding Accomplishment award.
"... None of our competitors has access to such strong biased-random test program generation ... The success of many PowerPC processor tape-outs rests in no small part on Genesys-Pro ..."
IBM VP Microprocessor Development
"The ultimate measure of our success and the impact that Genesys-Pro had, was that the DD 1.0 [Xbox processor] chip was able to run a game application within one week of initial Power On. It is unlikely this could have been accomplished without Genesys- Pro."
IBM's Xbox processor Program Manager
History and Related Tools
For over two decades, the researchers in the IBM Haifa Research Lab have been developing technologies and solutions for functional verification. Genesys Pro is the fourth-generation architectural-level test case generator. Its predecessor, Genesys, was the backbone for early PowerPC designs and used in other commercial designs based on a variety of architectures, e.g., the x86, ARM, and ST100/ST200 VLIW processors. Leveraging the experience from Genesys, and mainly from the Genesys model-based approach, Genesys Pro was built from scratch and added significant new capabilities, including the new constraint satisfaction engine and the expressive test template language.
Additional test generator tools developed in the department include:
- Threadmill: post-silicon test case generator
- FPGen: coverage-driven test case generator specifically targeting IEEE floating point units