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October 27-30, 2008
Organized by IBM Haifa Research Lab
Verification Challenges of Low-Power Design
Karen Yorav, IBM HRL
Power consumption is an important consideration in modern chip design. Some claim that today, power consumption is just as important as speed. An increased demand for portability and the high expense of powering large server farms makes low power consumption important for a wide range of products. Moreover, with the move into sub-micron process technology, the power consumption of a single circuit element has increased dramatically. Many power saving techniques are purely electrical, such as changing the type of transistor used. Other techniques, while electrical, can be understood at the logical level. Among them are multiple power domains, dynamic frequency/voltage scaling, clock gating, and power gating. In addition to the physical design challenges ( i.e., getting the electronics right), each of these techniques adds a new dimension to the functional verification problem. In this talk I will explain these design techniques and discuss the verification challenges they present. The talk will assume no previous knowledge of electronic design.
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