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October 27-30, 2008
Organized by IBM Haifa Research Lab
Moore's Law v. Verification Complexity
Jason Baumgartner
More than 40 years ago, Moore's Law predicted a periodic doubling of the number of transistors per cost-effective integrated circuit. The complexity class of formal verification superficially implies that this trend mandates a periodic exponential growth of verification complexity. However, given an appropriate verification strategy, the modularity and growth of data width / memory size often used to consume this capacity does not necessarily pose a barrier to verification scalability. Nonetheless, the roadmap by which Moore's Law has defied countless "doomsday predictions" has triggered various design characteristics which do entail substantial verification complexity. Among these, the increase in circuit density has encouraged an increase in clock speed - often realized through heavy pipelining and circuit optimizations which directly increase verification complexity. Additionally, with higher circuit density comes higher power density and consumption, triggering a slew of intricate design techniques to cope with this trend. Furthermore, as data widths and depths continue to grow, coupled with an increase in soft error rates due to shrinking feature sizes, the need for and complexity of error detection and correction logic has grown. For a variety of reasons, these design characteristics often must be directly modeled and intertwined directly with the core design functionality description. The need for reliable post-silicon analysis further intertwines debug logic with this increasingly complex circuit-like design description, overall avalanching into a substantial verification mess.
In this talk, we discuss the impact of these byproducts of Moore's Law on the verification process. We additionally discuss numerous verification techniques (algorithmic and methodological) which attempt to overcome these challenges. We finally introduce emerging design techniques which promise to help offset this complexity avalanche without jeopardizing necessary design characteristics of speed, performance, and testability.
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