A set of innovations showing a future beyond nanosheet devices and copper interconnects were presented by IBM researchers at this year’s IEDM conference lay the groundwork for a near future where semiconductors with nodes at 1nm and beyond are possible.
Our world is powered by computer chips. Look around you right now, and there are inevitably countless devices running on semiconductors, from the obvious ones like your computer and phone, all the way through to things like your toaster and your car. What we demand of our devices is constantly increasing, meaning we need more powerful and energy-efficient chips.
For years, the pace of innovation in semiconductors has been driven by Moore’s Law, which states that about every two years, the number of transistors on a microchip will double. This prediction has slowed in recent years, as we’ve butted up against the physical limits of the material used to develop chips. In 2021, IBM Research unveiled the world’s first 2 nm node chip, the smallest in the world. That followed a string of innovations in recent years that have consistently shrunk down chip nodes. While there are still several years left before the industry gets the most out of the 2 nm breakthrough, IBM Research is always looking at what’s beyond the horizon.
We have identified two major breakthroughs that we believe will lead us down a path to designing computer chip nodes targeting for 1nm and beyond. Both have been presented at this year’s IEEE International Electron Devices Meeting (IEDM) in San Francisco.
In computer chips, the wiring between components in a semiconductor is called an interconnect. It’s how electrical current flows between individual transistors, between memory, processing units, and any other components in a chip — the more effective interconnects are at allowing that transfer to happen, the more efficient the chip can be. For decades, state-of-the-art interconnects between chips were made of aluminum — until 1997.
That year, IBM announced that it could make microchips smaller and faster by using copper instead of aluminum for interconnects. Copper wires conduct electricity with about 40% less resistance than aluminum wires, which translates to about a 15% increase in processing speed. For the last few decades, this seismic shift has resulted in copper becoming the industry standard for interconnects.
But as is the case with silicon, we’re getting down to the physical limits of what we can do with copper wiring. In the path to 1nm and beyond, we believe the effectiveness of tiny copper wires begins to fade. IBM researchers have been looking for what comes after copper, and the answer may be found in the metal ruthenium.
Copper interconnects have always required a barrier liner material to form a proper wiring structure. As devices shrink, the amount of space available for the copper wiring, and the liner material becomes smaller. With ruthenium, which can scale to 1nm node and beyond and still be an effective conductor, there’s no need for a liner, which helps save on space. Ruthenium formed by subtractive patterning method also can potentially be used for a new type of interconnect integration scheme, called top-via integration. In this scenario, the interconnecting via is formed on the top of the wire, rather than below the wire, allowing for successive wires and self-aligned vias to be formed for the most critical interconnect layers. Additionally, the embedded air gaps formed robustly by such top-via integration that result in reduced interconnect parasitic capacitance would also contribute to faster and lower power consumption chips.
The team at IBM has been working on the potential of ruthenium for over three years now, and there’s a strong belief that this noble metal is a serious contender to replace copper. The researchers used extreme ultraviolet lithography (EUV) double patterning to create test structures on existing machines they have in Albany. This has enabled this breakthrough with current generation EUV machines available today and will be extendable to the next-generation High-NA EUV machines. We call this “Interconnect 3.0” to reflect the new era beyond aluminum and copper.
Over the next few years, the researchers plan to refine their testing to get to a point where they’ve produced completely viable chips. But they believe the path to “Interconnect 3.0” is clear with ruthenium for 1nm nodes and beyond.
At last year’s IEDM conference, IBM unveiled VTFET, a new way of designing semiconductors. With VTFET, transistor components are stacked vertically on top of each other, rather than laterally, as has been the standard for designing chips since the dawn of the Computer Age. This drastically increases the number of transistors that one could fit on a single chip, in much the same way that a city of skyscrapers has a far greater population density than a suburb of townhomes.
At this year’s IEDM conference, the team announced that they have already achieved 90% of the device performance of the technology target on the best chips demonstrated in actual silicon hardware. The group’s research shows it’s possible to scale VTFET designs well beyond the performance of the state-of-the-art 2-nanometer node nanosheet designs, which IBM Research first unveiled in 2021.
While the nanosheet technology used for the 2nm chips still has many years of use ahead of it — most companies have yet to even release commercially viable 2nm chips — IBM Research is always concerned with what comes next.
A year ago, we asserted that the VTFET design represents a huge leap forward toward building next-generation transistors that will enable a trend of smaller, more powerful, and energy-efficient devices in the years to come. And now, it’s clear from the latest silicon hardware results that VTFET has the performance capabilities to back up those claims. In the same way that we argued back in 2015 that to produce 7nm chips at scale, the industry would have to adopt EUV technology — which it now has been the industry standard. Similarly, in 2017, IBM Research said that nanosheet device structure would be the next device architecture needed beyond FinFET to produce smaller and more efficient devices at scale, which the industry has now adopted for 3nm and 2nm nodes. We believe VTFET to be a viable option for future generations of innovative chip designs in the post-nanosheet era.
Marrying the space and efficiency gains of VTFET with the potential of subtractive ruthenium wires with top-via enabled by EUV double patterning for interconnects, we see a long path to even smaller, more efficient devices ahead in 1nm nodes and beyond.